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February 26, 2003


Dr. Alain Diebold
International SEMATECH
"Metrology and Characterization Requirements and Challenges for the Nano-World of Integrated Circuits"

Abstract. Silicon semiconductor devices have entered the nanotechnology era.  New materials and processes have extended traditional Complementary Metal Oxide Semiconductor (CMOS) transistor technology. Despite this success, new transistor designs will be required during the next 10 years, and potentially new approaches to switching devices may be needed in 15 years. This makes understanding the metrology requirements of the semiconductor industry is a difficult task. The Metrology Roadmap of the International Technology Roadmap for Semiconductors provides considerable insight, and it will serve as a key reference for this discussion.  Starting in 2001, a new section discussing Emerging Research Devices provides a first reference for understanding metrology needs for the future.  The timing of the break between traditional planar CMOS and the first steps beyond are a topic of considerable speculation.  That makes the timing of future circuits based devices such as single electron transistors more difficult to predict.  Non- the - less, the 2003 Metrology Roadmap will contain a section on this topic. 

In this talk, metrology and characterization challenges including materials characterization, in-line metrology, and integrated metrology for near term and longer term future generations of integrated circuits based on planar CMOS will be discussed. Metrology challenges and potential measurement methods for the key process areas of lithography, front end (transistor and capacitor) processes, and on-chip interconnect will be described.  An overview of the materials characterization being used to develop emerging research devices will provide a long term view into the future.

Critical dimension (CD) measurement is the most visible of the key requirements for lithography metrology.  In reviewing the presently used methods of CD-SEM, scatterometry, and CD-AFM, one finds the need for development of a method capable of meeting long term needs. The status and future of existing methods along with the proposed 200 kV CD-SEM will be described.   
The measurement of the new high k gate stack will be emphasized in the discussion of front end processes metrology.  Physical and electrical metrology methods will be described along with the accompanying materials characterization. The recent consensus method for measuring thin dielectric layers by high angle annular dark field STEM will be presented. Other methods such as Medium Energy Ion Scattering are under utilized. 
Interconnect metrology must address both the control of porous low k layers and the barrier/seed copper, and electroplated copper including control of chemical mechanical polishing.  The ability to measure voids in copper lines will be described.  The various methods of measuring pores in low k will also be presented.

Vanderbilt University